Toshiba offers a "structured» ASIC as an alternative to FPGA

Company Toshiba Electronics Europe (TEE) has announced the availability of technology for European customers Structured Array. This technology allows the use of specialized chips (ASIC) as an alternative to field programmable gate array (FPGA). This ensures proper ASIC gain in cost and power consumption, but the time required to obtain the final product is much smaller than with conventional ASIC.

Underlying Structured Array technology is licensed from BaySand. The secret lies in accelerating the development of chip-with pre-formed blocks, which can be configured with minimal effort using custom masks for metallization layers. In particular, among the blocks is optimized gate arrays and memory. Minimizing the number of metallization layers to be developed for specialized chip, according to the manufacturer, has reduced the time of receipt of engineering samples of up to five weeks.

As stated, single-chip system, built on the basis of "structured» ASIC, are cheaper than the FPGA, have lower power consumption and can be designed for higher frequencies. At the same time, in their design, you can use the data collected in the design of FPGA. It is compatible with FPGA-level memory architecture, and input-output, and at the level of housing and conclusions that enables new ASIC as a direct replacement for the FPGA.

TEE now offers solutions designed to produce 65-nanometer technology, with up to 30 million gates, 20 Mbit SRAM and up to 1200 lines of input-output. Customers can integrate interfaces LVDS and DDR. Transceivers with a capacity up to 6.5 Gb / s in the process of development. In addition, the manufacturer plans to develop transceiver with up to 12.5 Gbit / s, and the development of 40 nm.

Source: TEE